`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 06/19/2024 04:36:57 PM
// Design Name: 
// Module Name: PWM_Logic
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module PWM_Logic(
    input S_AXI_ACLK,
    input wire [31:0] PWM0_Value,
    input wire [31:0] PWM1_Value,
    input wire [31:0] PWM2_Value,
    input wire [31:0] PWM3_Value,
    input wire [31:0] Period,
    output reg [3:0] PWM_Out
    );
    reg [31:0] counter=32'd0;

    always @(posedge S_AXI_ACLK) begin
        counter <= counter + 32'd1;
        if(counter>Period) begin
            counter<=32'd0;
        end    
    end

    always @(posedge S_AXI_ACLK) begin
        if(counter<PWM0_Value) begin
            PWM_Out[0] <= 1'b1;
        end else begin
            PWM_Out[0] <= 1'b0;
        end

        if(counter<PWM1_Value) begin
            PWM_Out[1] <= 1'b1;
        end else begin
            PWM_Out[1] <= 1'b0;
        end

        if(counter<PWM2_Value) begin
            PWM_Out[2] <= 1'b1;
        end else begin
            PWM_Out[2] <= 1'b0;
        end

        if(counter<PWM3_Value) begin
            PWM_Out[3] <= 1'b1;
        end else begin
            PWM_Out[3] <= 1'b0;
        end
    end
endmodule
